Report Board
ARM / QCOM / INTC / AMD: Four Chip Capacity Models
A DYOR capacity map for Arm, Qualcomm, Intel, and AMD, separating IP licensing, fabless SoCs, IDM manufacturing, and advanced packaging constraints.
Where the capacity actually comes from
Arm, Qualcomm, Intel, and AMD use the word capacity very differently: IP royalties, foundry allocation, owned fabs, and advanced-packaging throughput.
Arm
Arm has no disclosed owned wafer-start base. The AGI CPU uses TSMC 3nm and expands Arm into deliverable silicon, but units and wafer allocation are not disclosed.
Qualcomm
Core QCT ICs are mostly fabless. RFFE modules and RF filters have front-end and back-end operations in Germany, Singapore, and China. Disclosed evidence is commitments and risk, not allocation.
Intel
Intel is the only one here with large-scale owned leading-edge logic manufacturing and advanced packaging. Its own filing shows capacity is being recalibrated against demand.
AMD
AMD's advanced-product ceiling is a combined function of TSMC, advanced packaging, HBM, substrates, and OSAT partners. AMD's own capex does not represent its capacity ceiling.
A Reviewable Logic Chain
Each card stays open and maps one transmission node without collapsible controls or pseudo-precise scores.
Arm
Arm supply is not an owned fab base. It is CPU/GPU/system IP, licenses, royalties, and customer chip design cycles. The AGI CPU is the exception because it moves Arm into production silicon.
Qualcomm
Qualcomm relies on TSMC, Samsung, GlobalFoundries and OSAT partners such as ASE, Amkor, SPIL, and STATSChipPAC for most QCT ICs, while retaining some owned RF operations.
Intel
Intel controls the largest physical capacity base, but the 2025-2026 problem is usable supply, yield, utilization, and external foundry customer validation on Intel 18A and beyond.
AMD
AMD's CPU/GPU/AI ramp is a function of TSMC leading-edge wafers, CoWoS/SoIC, HBM, substrates, and OSAT delivery.
Company / source / public proxy / sufficiency
Customer-level wafer allocation and CoWoS allocation are not public. The amounts below are purchase commitments, revenue, official capacity, or manufacturing footprint proxies, not actual allocated output.
| Company | Where capacity comes from | Ticker | Public quantifiable proxy | Sufficiency | Bottleneck / note |
|---|---|---|---|---|---|
| Arm | Primarily CPU/GPU/system IP licensing and royalties; AGI CPU uses TSMC 3nm and adds packaging, test, cloud, and OEM ecosystem dependencies. | ARM | FY2026 revenue $4.92B; royalty revenue $2.61B; 350B+ cumulative Arm-based chip ecosystem claim. AGI CPU units/wafer allocation undisclosed. | IP supply is ample; AGI CPU ramp is unproven. | Arm is not mainly a foundry-capacity story. It becomes one only where Arm directly ships silicon such as the AGI CPU. |
| Qualcomm | Most QCT ICs are built by TSMC, Samsung, and GlobalFoundries; ATMP by ASE, Amkor, SPIL, and STATSChipPAC; RFFE/RF filters have owned operations. | QCOM | FY2025 IC purchase obligations $15.1B, $10.5B due within 12 months; multi-year capacity advances $1.9B; Q2 FY2026 QCT revenue $9.076B. | Core mobile/auto/IoT supply looks broadly workable; data-center AI is not proven publicly. | Q3 FY2026 guidance reflected memory supply/pricing pressure on handset OEM demand. Leading-edge and OSAT exposure remains Asia-heavy. |
| Intel | Owned fabs in Oregon, Arizona, Ireland, and Israel; owned/internal assembly, test, and advanced packaging in China, New Mexico, Vietnam, and Malaysia. | INTC | No total wafer-start disclosure. 2025 key fab/ATMP footprint disclosed. Q1 2026 revenue $13.6B; Intel Foundry revenue $5.4B before eliminations. | Most controlled physical capacity, but advanced-node usable supply is not fully sufficient. | The verification point is Intel 18A ramp, Intel 7/3 supply, New Mexico/Malaysia packaging, and external foundry wins. |
| AMD | Advanced CPU/GPU/AI wafers mainly from TSMC; some 12/14nm supply from GlobalFoundries; ATMP via Tongfu JVs, SPIL, KYEC and other Asia-Pacific partners. | AMD | FY2025 unconditional commitments $12.2B, $8.5B in FY2026; Q1 2026 revenue $10.3B; TSMC 2025 annual capacity exceeded 17M 12-inch equivalent wafers. | CPU supply is more manageable; AI accelerator upside is not fully sufficient. | The MI300/MI350/MI400/MI450 ceiling is driven by TSMC advanced nodes, CoWoS/SoIC, HBM, substrates, and board-level integration. |
Semiconductor capacity map · As of 2026-05-22
Earnings releases, announcements, filings, estimate tables, and reviewable sources.
- Core signal
- TSMC 17M+ 12-inch-equivalent annual capacity, Qualcomm $15.1B IC purchase obligations, AMD $12.2B unconditional commitments, Intel 18A and internal wafer constraints, Arm AGI CPU on TSMC 3nm
- Current read
- Intel has the most physical capacity under its own control, but the bottleneck is 18A/Intel 7/Intel 3 usable supply and utilization. AMD is the most exposed to external AI accelerator bottlenecks. Qualcomm's core mobile/auto/IoT supply chain is more mature, while its data-center AI ramp lacks public capacity proof. Arm's core IP business is not wafer-start constrained, except for the new AGI CPU silicon path.
- Next question
- Is the scarce resource wafers, advanced packaging, HBM, or each company's own manufacturing execution?
Arm's core capacity is not fabs; it is customer design throughput and royalty ecosystem scale. The AGI CPU is the new silicon exception.
Qualcomm core IC capacity comes from TSMC, Samsung, GlobalFoundries, and OSAT partners; owned manufacturing mainly covers RF/RFFE.
Intel controls the most physical capacity, but the 2026 proof point is Intel 18A ramp, Intel 7/3 supply, and advanced packaging.
AMD's AI accelerator upside depends on more than TSMC wafers: CoWoS/SoIC, HBM, substrates, and OSAT delivery all matter.
Arm AGI CPU customer, shipment, and cloud/server deployment disclosures in 2H 2026.
Qualcomm AI200 2026 and AI250 2027 disclosures around foundry, packaging, HBM, or customer capacity commitments.
Intel Panther Lake, Clearwater Forest, and Core Series 3 milestones for 18A yield, cost, and external foundry wins.
AMD MI350/MI400/MI450 supply cadence and public clues on TSMC CoWoS/SoIC, HBM, and substrate allocation.